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SGRAM
FEATURES
O JEDEC standard 3.3V power supply O LVTTL compatible with multiplexed address O Dual bank / Pulse RAS O MRS cycle with address key programs
M32L1632512A
256K x 32 Bit x 2 Banks
Synchronous Graphic RAM
GENERAL DESCRIPTION
The M32L1632512A is 16, 777, 216 bits synchronous high data rate Dynamic RAM organized as 2 x 262, 144 words by 32 bits, fabricated with ESMT's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies , programmable burst length, and programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. Write per bit and 8 columns block write improves performance in graphic systems.
O O O O O O
- CAS Latency ( 2, 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM 0-3 for byte masking Auto & self refresh 32ms refresh period (2K cycle) 100 pin QFP
Graphic Features
O SMRS cycle
ORDERING INFORMATION
- Load mask register - Load color register O Write Per Bit O Block Write (8 Columns)
Part NO. M32L1632512A-5Q M32L1632512A-5SQ M32L1632512A-6Q M32L1632512A-6SQ M32L1632512A-7Q M32L1632512A-7SQ M32L1632512A-8Q M32L1632512A-8SQ Cycle time 5ns 5ns 6ns 6ns 7ns 7ns 8ns 8ns Clock Access tRDL Frequency time@CL=3 (clk) 200MHz 200MHz 166MHz 166MHz 143MHz 143MHz 125MHz 125MHz 4.5ns 4.5ns 5.5ns 5.5ns 6.0ns 6.0ns 6.5ns 6.5ns 1 2 1 2 1 2 1 2
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FUNCTIONAL BLOCK DIAGRAM
DQMi BLOCK WRITE CONTROL LOGIC CLK CKE CS RAS CAS WE DSF DQMi SERIAL COUNTER COLUMN ADDRESS BUFFER TIMING REGISTER COLUMN MASK
LATENCY & BURST LENGTH
M32L1632512A
MASK REGISTER WRITE CONTROL LOGIC MASK MUX COLOR REGISTER
INPUT BUFFER
DQMi
DQi (i=0~31)
PROGRAMING REGISTER
COLUMN DECORDER
SENSE AMPLIFIER
256Kx32 CELL ARRAY
256Kx32 CELL ARRAY
ROW DECORDER BANK SELECTION ROW ADDRESS BUFFER REFRESH COUNTER
ADDRESS REGISTER CLOCK ADDRESS(A0~A10)
PIN CONFIGURATION (TOP VIEW)
DQM3 VDDQ DQ15 DQ25 DQ28 DQ27 DQ26 DQ24 DQ14 VDDQ VSSQ DQM1 DQ11 DQ13 DQ12 VDDQ DQ10 VDDQ VSSQ VSSQ DQ 9 DQ 8 CKE CLK DSF VDD N. C VSS N. C A9
80
79
78
77
76
75
74
71
73
72
70
69
68
67
66
65
64
63
62
61
60
59 58
57
54
53
56
55
DQ29 VSSQ DQ30 DQ31 VSS N. C N. C N. C N. C N. C N. C N. C N. C N. C N. C VDD DQ 0 DQ 1 VSSQ DQ 2
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 10 0 10 11 12 13 14 15 16 17 18 19 20 21 23 24 27 28 22 25 26 29 30 1 2 3 4 5 6 7 8 9 100 P in Q FP Type mm P itc h
52
51
50 49 48 47 46 45 44 43 F o rw a rd 20 0 .6 5 x 14 42 41 40 39 38 37 36 35 34 33 32 31
A7 A6 A5 A4 VSS N. C N. C N. C N. C N. C N. C N. C N. C N. C N. C VDD A3 A2 A1 A0
m m p in
DQ 6
DQ 7
VDDQ
VSSQ
CS BA(A10)
VSSQ
DQ3 VDDQ
DQ4
DQ5
DQ16
DQ17
DQ18
DQ19 VDDQ
DQ21 VSSQ
WE
DQM0
DQM2
DQ20
DQ23
VDDQ
CAS
DQ22
RAS
VDD
VSS
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OUTPUT BUFFER
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PIN DESCRIPTION
PIN CLK CS CKE NAME System Clock Chip Select Clock Enable INPUT FUNCTION
M32L1632512A
Active on the positive going edge to sample all inputs Disables or enable device operation by masking or enabling all inputs except CLK, CKE and DQMi Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one clock+ tss prior to new command. Disable input buffers for power down in standby. Row / column addresses are multiplexed on the same pins. Row address : RA0~RA9, column address : CA0~CA7 Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column address on the positive going edge of the CLK With CAS low. Enables column access. Enables write operation and Row precharge. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte Masking) Data inputs/outputs are multiplexed on the same pins. Enables write per bit, block write and special mode register set.
A0 ~ A9 A10(BA) RAS
Address Bank Select Address Row Address Strobe
CAS
Column Address Strobe
WE DQMi DQi DSF VDD/VSS VDDQ/VSSQ
Write Enable Data Input/Output Mask Data Input/Output Define Special/ Function Power Supply/ Ground Data Output Power/Ground
ABSOLUTE MAXIMUM RATINGS (Voltage referenced to VSS)
Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 Unit V V i W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
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DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V)
Parameter Supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current Output Loading Condition Symbol VDD, VDDQ VIH VIL VOH VOL IIL IOL Min 3.0 2.0 -0.3 2.4 -5 -5 Typ 3.3 3.0 0 See Fig 1 Max 3.6 VDD+0.3 0.8 0.4 5 5
M32L1632512A
Unit V V V V V A A
Note
Note 1 IOH = -2mA IOL = 2mA Note 2 Note 3
Note: 1. VIL(min) = -1.5V AC (pulse width 5ns) 2. Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V. 4. Dout is disabled, 0V VOUT VDD.
CAPACITANCE (VDD/VDDQ = 3.3V, TA = 25 C , f = 1MHZ)
Parameter Input capacitance (A0 ~ A10) Input capacitance (CLK, CKE, CS , RAS , CAS , WE , DSF& DQM0-3) Data input/output capacitance (DQ0 ~ DQ31) COUT 5 pF Symbol CIN1 CIN2 Min Max 4 4 Unit pF pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter Decoupling Capacitance between VDD & VSS Decoupling Capacitance between VDDQ & VSSQ Symbol CDC1 CDC2 Value 0.1+0.01 0.1+0.01 Unit uF uF
*Note: 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other. All VSS pins are connected in chip. All VSSQ pins are connected in chip.
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DC CHARACTERISTICS
Parameter Symbol Test Condition Burst Length = 1 ICC1 CAS
M32L1632512A
Recommended operating condition unless otherwise noted, TA = 0 to 70 C VIH(min) /VIL(max) =2.0V/0.8V
Version Unit Note
Latency -5/5S -6/6S -7/7S -8/8S Operating Current (One Bank Active) 3 2 230 230 2 2 35 210 210 2 2 35 195 195 2 2 35 170 170 2 mA 2 35 mA 15 3 3 60 15 3 3 60 15 3 3 60 15 3 3 60
tRC tRC(min), tCC tCC(min)
IOL = 0 mA
mA
1
ICC2P CKE VIL(max), tCC = 15ns Precharge Standby Current in power-down mode ICC2PS CKE VIL(max), CLK VIL(max), tCC = Precharge Standby Current in non power-down mode ICC2N CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns ICC2NS CKE VIH(min), CLK VIL(max), tCC = input signals are stable Active Standby Current in power-down mode ICC3P CKE VIL(max), tCC = 15ns ICC3PS CKE VIL(min), CLK VIL(max), tCC = ICC3N CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns ICC3NS CKE VIH(min), CLK VIL(max), tCC = input signals are stable Operating Current (Burst Mode) ICC4 IOL = 0 mA, Page Burst All Banks Activated, tCCD = tCCD
(min)
mA
Active Standby Current in non power-down mode (One Bank Active)
mA
20 230 230 190 190 2 220
20 210 210 170 170 2 200
20 195 195 160 160 2 190
20 170 mA 1, 2 170 150 mA 3 150 2 180 mA mA 4
3 2
Refresh Current
ICC5
tRC tRC(min)
CKE 0.2V
3 2
Self Refresh Current Operating Current (One Bank Block Write)
ICC6 ICC7
tCC tCC(min), IOL = 0 mA, tBWC(min)
*Note : 1. Measured with outputs open. 2. Assumes minimum column address update cycle tCCD(min). 3. Refresh period is 32ms. 4. Assumes minimum column address update cycle tBWC(min).
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Parameter AC Input levels Input timing measurement reference level Input rise and fall-time (See note3) Output timing measurement reference level Output load condition Value 1.4V
M32L1632512A
AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, TA = 0 to 70 C )
VIH/VIL = 2.4V/0.4V
tR/tF = 1ns/1ns
1.4V See Fig. 2
3.3V 1200e Output 870 VOH (DC) =2.4V , IOH = -2 mA VOL (DC) =0.4V , IOL = 2 mA 30pF Output
VREF = 1.4V 50
Z0 =50
e
e
e
30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
-5/5S Parameter CAS latency =3 CAS latency =2 CLK to valid CAS latency =3 output delay CAS latency =2 Output data CAS latency =3 hold time CAS latency =2 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output In Hi-Z CAS latency =3 CAS latency =2 Symbol Min Max Min Max Min Max Min Max CLK cycle time 5 7.5 2 2 2 2 2 1 1 5 5 6 8 2 2 2 2 2 1 1 5.5 6 7 10 2 2 2.5 2.5 2 1 1 6 7 8 12 2 2 3 3 2.5 1 1 6.5 8 -6/6S -7/7S -8/8S Unit Note
tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ
1000 4.5 5
1000 5.5 6
1000 6 7
1000 6.5 8
ns ns ns ns ns ns ns ns ns ns
1 1, 2 2 3 3 3 3 2
* All AC parameters are measured from half to half.
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M32L1632512A
*Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2 - 0.5) ns should be added to the parameter. 3. Assumed input rising and falling time (tr & tf) = 1ns. If tr & tf is longer 1ns, transient time compensation should be considered. i.e., [(tr + tf)/2 - 1] ns should be added to the parameter.
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to new col. address delay Last data in to row precharge Block write data-in to PRE command delay Block write data-in to Active (REF) command period (Auto precharge) Last data to burst stop Col. Address to col. Address delay Block write cycle time Number of valid Output data Symbol -5 -5S 10 15 15 40 -6 12 18 18 40 100 55 60 1 1 10 25 2 1 12 30 1 1 2 2 2 1 2 2 2 1 14 35 2 1 16 40 2 63 72 Version -6S -7 -7S 14 20 21 42 -8 -8S 16 20 24 48 ns ns ns us ns CLK CLK ns ns CLK CLK CLK CLK 2 3 4 5 1 2 2 Unit Note 1 1 1 1
tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tCDL(min) tRDL(min) tBPL(min) tBAL(min) tBDL(min) tCCD(min) tBWC(min)
CAS latency = 3 CAS latency = 2
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change except block write cycle. 4. This parameter means minimum CAS to CAS delay at block write cycle only. 5. In case of row precharge interrupt, auto precharge and read burst stop.
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FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE
M32L1632512A-5Q ( * : -5SQ )
Frequency 200 MHz(5.0ns) 166 MHz(6.0ns) 143 MHZ(7.0ns ) 125 MHZ(8.0ns ) CAS Latency 3 3 3 2
M32L1632512A
(Unit : number of clock)
tRC
55ns 11 10 8 7
tRAS
40ns 8 7 6 5
tRP
15ns 3 3 3 2
tRRD
10ns 2 2 2 2
tRCD
15ns 3 3 3 2
tCCD
5ns 1 1 1 1
tCDL
5ns 1 1 1 1
tRDL
5ns 1 1 1 1
* tRDL
10ns 2 2 2 2
M32L1632512A-6Q ( * : -6SQ )
Frequency 166 MHz(6.0ns) 143 MHZ(7.0ns ) 125 MHZ(8.0ns ) 100 MHZ(10.0ns ) CAS Latency 3 3 2 2
(Unit : number of clock)
tRC
60ns 10 9 8 6
tRAS
40ns 7 6 5 4
tRP
18ns 3 3 3 2
tRRD
12ns 2 2 2 2
tRCD
18ns 3 3 3 2
tCCD
6ns 1 1 1 1
tCDL
6ns 1 1 1 1
tRDL
6ns 1 1 1 1
* tRDL
12ns 2 2 2 2
M32L1632512A-7Q ( * : -7SQ )
Frequency 143 MHZ(7.0ns ) 125 MHZ(8.0ns ) 100 MHZ(10.0ns ) 83 MHZ(12.0ns ) CAS Latency 3 3 2 2
(Unit : number of clock)
tRC
63ns 9 8 7 6
tRAS
42ns 6 6 5 4
tRP
21ns 3 3 3 2
tRRD
14ns 2 2 2 2
TRCD
20ns 3 3 2 2
tCCD
7ns 1 1 1 1
tCDL
7ns 1 1 1 1
tRDL
7ns 1 1 1 1
* tRDL
14ns 2 2 2 2
M32L1632512A-8Q ( * : -8SQ )
Frequency 125 MHZ(8.0ns ) 100 MHZ(10.0ns ) 83 MHZ(12.0ns ) 75 MHZ(13.4ns ) CAS Latency 3 3 2 2
(Unit : number of clock)
tRC
72ns 9 8 6 6
tRAS
48ns 6 5 4 4
tRP
24ns 3 3 2 2
tRRD
16ns 2 2 2 2
tRCD
20ns 3 2 2 2
tCCD
8ns 1 1 1 1
tCDL
8ns 1 1 1 1
tRDL
8ns 1 1 1 1
* tRDL
16ns 2 2 2 2
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SIMPLIFIED TRUTH TABLE
COMMAND Register
Mode Register set Special Mode Register Set
M32L1632512A
CKEn-1 CKEn H H L H H H H H X H
Entry
CS
RAS CAS L L H X L H H H H L H X X H X V X X H X L L H X H L L L H H H X X H X V X H X
WE
DSF DQM A10 A9 L H X X X X X X X X X X X X X V X V X X X V X L H X V V V V
A8~A0
Note
L L L H
L H H X H H L L L L H X X H X V X H
OP CODE X X Row Address L H L H L H X X Column Address Column Address Column Address
1, 2
1, 2, 7
Auto Refresh Refresh Self Refresh Bank Active & Row Addr.
Read & Column Address Write & Column Address Block Write & Column Address
L H X X X X X X L H L
L X L H L L H L L X X X
3 3 3 3 4, 5 4,5,9 4 4, 6 4, 5
4,5,6,9
Exit
Write Per Bit Disable Write Per Bit Enable Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Bank Selection Both Banks
L L L L L L L
4, 5
4,5,6,9
Burst Stop
Precharge
7
H Entry Exit Entry H L H
Clock Suspend or Active Power Down
H X L
Precharge Power Down Mode Exit DQM No Operation Command L H H
H L H L
8
H
X H X
X
X
(V = Valid, X = Don't Care. H = Logic High, L = Logic Low )
Note : 1.OP Code : Operand Code A0~A10 : Program keys. (@ MRS) A5, A6 : LMR & LCR select. (@ SMRS) Color register exists only one per DQi which both banks share. So does Mask Register. Color or mask is loaded into chip through DQ pin. 2.MRS can be issued only at both banks precharge state. SMRS can be issued only if DQ's are idle. A new command can be issued at the next clock of MRS/SMRS.
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M32L1632512A
3.Auto refresh functions as same as CBR refresh of DRAM. The automatical precharge without Row precharge of command is meant by "Auto". Auto/self refresh can be issued only at both banks precharge state. 4.A10 : Bank select address. If "Low" at read, (block) write, Row active and precharge, bank A is selected. If "High" at read, (block) write, Row active and precharge, bank B is selected. If A9 is "High" at Row precharge, A10 is ignored and both banks are selected. 5.It is determined at Row active cycle. whether Normal/Block write operates in write per bit mode or not. For A bank write, at A bank Row active, for B bank write, at B bank Row active. Terminology : Write per bit = I/O mask (Block) Write with write per bit mode = Masked (Block) Write 6.During burst read or write with auto precharge, new read/(block) write command cannot be issued. Another bank read/(block) write command can be issued at tRP after the end of burst. 7.Burst stop command is valid for all burst length. 8.DQM sampled at positive going edge of a CLK. masks the data-in at the very CLK (Write DQM latency is 0) but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2) 9.Graphic features added to SDRAM's original features. If DSF is tied to low, graphic functions are disabled and chip operates as a 16M SDRAM with 32 DQ's.
SGRAM vs SDRAM
SDRAM Function DSF SGRAM Function L MRS MRS H SMRS L Bank Active H Bank Active With Write per bit Enable L Normal Write Write H Block Write
Bank Active With Write per bit Disable If DSF is low. SGRAM functionality is identical to SDRAM functionality.
AE
SGRAM can be uesed as an unified memory by the appropriate DSF control SGRAM = Graphic Memory + Main Memory.
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address Function A10 RFU (Note2) A9 W.B.L A8 TM A7 A6 A5 CAS Latency A4 A3 BT A2 A1 A0
Burst Length
(Note1)
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Test Mode A8 0 0 1 1 A7 0 1 0 1 Type Mode Register Set Vendor Use Only A6 0 0 0 0 1 1 1 1 CAS Latency A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved 2 3 Reserved Reserved Reserved Reserved Burst Type A3 0 1 Type Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1
M32L1632512A
Burst Length A0 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 BT = 1 Reserved Reserved 4 8
Write Burst Length A9 0 1 Length Burst Single Bit
Reserved Reserved Reserved Reserved Reserved Reserved 256(Full) Reserved
(Note 3)
Special Mode Register Programmed with SMRS
Address Function A10 A9 X A8 A7 A6 LC A5 LM A4 A3 X A2 A1 A
Load Color A6 0 1 Function Disable Enable
Load Mask A5 0 1 Function Disable Enable (Note 4)
POWER UP SEQUENCE
1.Apply power and start clock, Attempt to maintain CKE = "H", DQM = "H" and the other pin are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 s. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 may be changed. The device is now ready for normal operation. Note : 1. RFU(Reserved for Future Use) should stay "0" during MRS cycle. 2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 3. The full column burst (256bit) is available only at Sequential mode of burst type. 4. If LC and LM both high (1), data of mask and color register will be unknown.
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BURST SEQUENCE (BURST LENGTH = 4)
Initial Address A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2 Sequential
M32L1632512A
Interleave 2 3 0 1 3 2 1 0
BURST SEQUENCE (BURST LENGTH = 8)
Initial address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 Sequential Interleave
PIXEL to DQ MAPPING (at BLOCK WRITE)
Column address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 3 Byte I/O31~ I/O24 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 2 Byte I/O23~ I/O16 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 1 Byte I/O15~ I/O8 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 0 Byte I/O7~ I/O0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
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DEVICE OPERATIONS
CLOCK (CLK) The clock input is used as the reference for all SGRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of setup and hold time around positive edge of the clock for proper functionality and Icc specifications.
M32L1632512A
ADDRESS INPUTS (A0~A9) The 18 address bits are required to decode the 262,144 word locations are multiplexed into 10 address input pins (A0~A9). The 10 bit row address is latched along with RAS and A10 during bank activate command. The 8 bit column address is latched along with CAS, WE and A10 during read or write command.
NOP and DEVICE DESELECT CLOCK ENABLE(CKE) The clock enable (CKE) gates the clock onto SGRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When both banks are in the idle state and CKE goes low synchronously with clock, the SGRAM enters the power down mode from the next clock cycle. The SGRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "tSS+1CLOCK" before the high going edge of the clock, then the SGRAM becomes active from the same clock edge accepting all the input commands. When RAS , CAS and WE are high, The SGRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS , CAS, WE , DSF and all the address inputs are ignored.
POWER-UP The following sequence is recommended for POWER UP 1.Power must be applied to either CKE and DQM inputs to pull them high and other pins are NOP condition at the inputs before or along with VDD (and VDDQ) supply. The clock signal must also be asserted at the same time. 2.After VDD reaches the desired voltage, a minimum pause of 200 microseconds is required with inputs in NOP condition. 3.Both banks must be precharged now. 4.Perform a minimum of 2 Auto refresh cycles to stabilize the internal circuitry. 5.Perform a MODE REGISTER SET cycle to program the CAS latency, burst length and
BANK SELECT (A10) This SGRAM is organized as two independent banks of 262, 144 words x 32 bits memory arrays. The A10 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. When A10 is asserted low, bank A is selected. When A10 is latched high, bank B is selected. The banks select A10 is latched at bank activate, read, write, mode register set and precharge operations.
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DEVICE OPERATIONS (Continued)
burst type as the default value of mode register is undefined. At the end of one clock cycle from the mode register set cycle, the device is ready for operation. When the above sequence is used for Power-up, all the outputs will be in high impedance state. The high impedance of outputs is not guaranteed in any other power-up sequence. cf.) Sequence of 4 & 5 may be changed. MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SGRAM. It programs the CAS latency, burst type, addressing, burst length, test mode and various vendor specific options to make SGRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SGRAM. The mode register is written by asserting low on CS , RAS , CAS, WE and DSF (The SGRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0~A9 and A10 in the same cycle as CS , RAS , CAS, WE and DSF going low is the data written in the mode register. One clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as both banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length field uses A0~A2, burst type uses A3, CAS latency (read latency from column address) A4~A6, A7~A8 and A10 are uses for vendor specific options or test mode use. And the write burst length is programmed using A9. A7~A8 and A10 must be set to low for normal SGRAM operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BANK ACTIVATE
M32L1632512A
The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank addresses, a row access is initiated. The read or write operation can occur after a time delay of tRCD (min) from the time of bank activation. tRCD (min) is the internal timing parameter of SGRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD (min) with cycle time of the clock and then rounding of the result to the next higher integer. The SGRAM has two internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of both banks immediately. Also the noise generated during sensing of each bank of SGRAM is high requiring some time for power supplies to recover before another bank can be sensed reliably. tRRD (min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS (min). Every SGRAM bank activate command must satisfy tRAS (min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS (max). The number of cycles for both tRAS(min) and tRAS (max) can be calculated similar to tRCD specification.
BURST READ The burst read command is used to access burst of data on consecutive clock cycles from an
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DEVICE OPERATIONS (Continued)
active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD (min) before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid for all burst length.
M32L1632512A
The write burst can also be terminated by using DQM for blocking data and precharging the bank "tRDL" after the last data input to be written into the active row. See DQM OPERATION also.
DQM OPERATION The DQM is used mask input and output operations. It works similar to OE during operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interrupts of write with read or precharge in the SGRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is required. DQM is also used for device selection and bus control in a memory system. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31. DQM masks the DQ's by a byte regardless that the corresponding DQ's are in a state of WPB masking or Pixel masking. Please refer to DQM timing diagram also.
BURST WRITE The burst write command is similar to burst read command, and is used to write data into the SGRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS , CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing may not have been completed yet. The writing can not complete to burst length. The burst write can be terminated by issuing a burst read and DQM for blocking data inputs or burst write in the same or the other active bank.
PRECHARGE The precharge is performed on an active bank by asserting low on CS , RAS , WE and A9 with valid A10 of the bank to be precharged. The precharge command can be asserted anytime after tRAS (min) is satisfy from the bank activate command in the desired bank. "tRP" is defined as the minimum time required to precharge a bank.
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DEVICE OPERATIONS (Continued)
The minimum number of clock cycles required to complete row precharge is calculated by dividing "tRP" with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by tRAS (max). Therefore, each bank has to be precharged within tRAS (max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to Power Down, Auto refresh, Self refresh and Mode register Set etc. is possible only when both banks are in idle state. AUTO REFRESH
M32L1632512A
AUTO PRECHARGE The precharge operation can also be performed by using auto precharge. The SGRAM internally generates the timing to satisfy tRAS (min) and "tRP" for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst read or burst write by asserting high on A9. If burst read or burst write command is issued with low on A9, the bank is left active until a new command is asserted. Once auto precharge command is given, no new command are possible to that particular bank until the bank achieves idle state.
The storage cells of SGRAM need to be refreshed every 32ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS , RAS and CAS with high on CKE and WE . The auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by tRC (min). The minimum number of clock cycles required can be calculated by driving tRC with clock cycle time and them rounding up to the next higher integer. The auto refresh command must be followed by NOP's until the auto refresh operation is completed. Both banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SGRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us or the burst of 2048 auto refresh cycles in 32ms.
SELF REFRESH The self refresh is another refresh mode available in the SGRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SGRAM. In self refresh mode, the SGRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption. The self refresh mode is entered from all banks idle state by asserting low on CS , RAS , CAS and CKE with high on WE . Once the self refresh mode is entered, only CKE state
BOTH BANKS PRECHARGE Both banks can be precharged at the same time by using Precharge all command. Asserting low on CS , RAS and WE with high on A9 after all banks have satisfied tRAS (min) requirement, performs precharge on both banks. At the end of tRP after performing precharge all, all banks are in idle state.
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DEVICE OPERATIONS (Continued)
being low matters, all the other inputs including clock are ignored to remain in the refresh. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of tRC before the SGRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to use burst 2048 auto refresh cycles immediately after exiting self refresh.
M32L1632512A
the condition that DQ's are idle. As in write operation, SMRS accepts the data needed through DQ pins. Therefore it should be attended not to induce bus contention. The more detailed materials can be obtained by referring corresponding timing diagram.
WRITE PER BIT Write per bit(i.e. I/O mask mode) for SGRAM is a function that selectively masks bits of data being written to the devices. The mask is stored in an internal register and applied to each bit of data written when enable. Bank active command with DSF=High enable write per bit for the associated bank. The mask used for write per bit operations is stored in the mask register accessed by SWCBR (Special Mode Register Set Command). When a mask bit=0, the associated data bit is unaltered when a write command is executed and the write per bit has been enable for the bank being written. No additional timing conditions. Write per bit writes can be either masking is the same for write per bit and non-WPB write.
DEFINE SPECIAL FUNCTION(DSF) The DSF controls the graphic applications of SGRAM. If DSF is tied to low, SGRAM functions as 256K x 32 x 2 Bank SDRAM. SGRAM can be used as an unified memory by the appropriate DSF command. All the graphic function mode can be entered only by setting DSF high when issuing commands which otherwise would be normal SDRAM commands. SDRAM functions such as RAS Active, Write and WCBR change to SGRAM functions such as RAS Active with WPB, Block Write and SWCBR respectively, see the sessions below for the graphic functions that DSF controls.
BLOCK WRITE SPECIAL MODE REGISTER SET(SMRS) There are two kinds of special mode registers in SGRAM. One is color register and the other is mask register. Those usage will be explained at "WRITE PER BIT" and "BLOCK WRITE" session. When A5 and DSF goes high in the same cycle as CS , RAS , CAS and WE going low, load color register is filled with color data for associated DQ's through the DQ pins. If both A5 and A6 are high at SMRS, data of mask and color cycle is required to complete the write in the mask register and the color register at LMR and LCR respectively. The next color of LMR and LCR, a new commands can be issued. SMRS, compared with MRS, can be issued at the active state under Block write is a feature allowing the simultaneous writing of consecutive 8 columns of data within a RAM device during a single access cycle. During block write the data to be written comes from the internal "color" register and DQ I/O pins are used for independent column selection. The block of column to be written is aligned on 8 column boundaries and is defined by the column address with the 3 LSB's ignored. Write command with DSF=1 enable block write for the associated bank. The block width is 8 column where column ="n" bits for by "n" part. The color register is the same width as the data port of the chip. It is width via a SWCBR where data present on the DQ pins is
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DEVICE OPERATIONS (Continued)
to be coupled into the internal color register. The color register provides the data masked by the DQ column select, WPB mask (if enable), and DQM byte mask. Column data masking (Pixel masking) is provided on an individual column basis for each byte of data. The column mask is driven on the DQ pins during a block write command. The DQ column mask function is segmented on a per bit basis (i.e. DQ [0:7] provided the column mask for data bits [0:7], DQ [8:15] provided the column mask for data bits [8:15], DQ0 masks column [0] for data bits[0:7], DQ9 masks column [1] for data bits[8:15], etc). Block writes are always non-burst independent of the burst length that has been programmed into to the mode register. If write per bit was enabled by the bank active command with DSF=1, then write per bit masking of the color register data is enabled. If write per bit was disabled by a bank active command with DSF=0, the write per bit masking of the color register data is disabled. DQM masking provides independent data byte masking during normal write operations, except that the control is extended to the consecutive 8 columns of the block write.
M32L1632512A
Timing Diagram to Illustrate tBWC
1. 2CLK Cycle Block Write
CLOCK CKE CS HI G H
RAS
CAS WE DSF 2 CLK BW
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Features 256K x 32 x 2 SGRAM Benefits Interface Synchronous
M32L1632512A
SUMMARY OF 2M Byte SGRAM BASIC FEATURES AND BENEFITS
Better interaction between memory and system without wait-state of asynchronous DRAM. High speed vertical and horizontal drawing. High operation frequency allows performance gain for SCROLL, FILL, and BitBLT. Pseudo-infinite row length by on-chip interleaving operation. Hidden row activation precharge. High speed vertical and horizontal drawing. High speed vertical and horizontal drawing. Programmable burst of 1, 2, 4, 8 and full page transfer per column address. Programmable burst of 1, 2, 4, 8 and full page transfer per column address. Switch to burst length of 1 at write without MRS. Compatible with Intel and Motorola CPU based system. Programmable CAS latency. High speed FILL, CLEAR, Text with color registers. Maximum 32 byte data transfer (e.g. for 8bpp : 32 pixels) with plane and byte masking functions. A and B bank share. Write-per-bit capability (bit plane masking). A and B bank share. Byte masking (pixel masking for 8bpp system) for data-out/in Each bit of the mask register directly controls a corresponding bit plane. Byte masking (pixel masking for 8bpp system) for color DQi.
Bank Page Depth /1 Row Total Page Depth Burst length (Read) Burst length (Write) Burst Type CAS Latency Block Write Color Register Mask Register
2ea 256 bit 2048 bytes 1, 2, 4, 8 Full Page 1, 2, 4, 8 Full Page BRSW Sequential & Interleave 2, 3 8 Column 1ea. 1 ea. DQM0~3
Mask function
Write per bit Pixel Mask at Block Write
BASIC FEATURE AND FUNCTION DESCRIPTION
1.CLOCK Suspend
1) C lock S uspended During W rite (BL=4) 2) Clock S uspe nded During Read (B L=4)
C LK CMD WR RD
CKE Internal CLK DQ( CL2) D0 D1 D1
Masked by CKE
Masked by CKE
D2
D3
Q0
Q1
Q2
Q3
DQ( CL 3)
D0
D2 N ot W r i tt en
D3
Q0
Q1
Q2
Q3
S us p end ed D ou t
*Note : CKE to CLK disable/enable=1 clock
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2. DQM Operation
1 )Writ e M ask (BL=4) 2)Rea d Mask (B L=4 )
M32L1632512A
CLK CMD
WR
RD
DQM
Maske d by D QM Masked by DQM Hi-Z
DQ(CL2)
D0
D1
D3
Q0
Q2
Q3
DQ( C L3 )
D0
D1
Hi-Z
D3
Q1
Q2
Q3
DQM t o Dat a-in Ma sk=0 CLK
DQM t o Da ta- o ut Ma sk= 2
3 ) DQM w i th cl co k suspe n de d ( Ful l Pa g e Rea d) Note2
CLK
CMD
RD
CKE
DQM
Hi-Z
DQ( C L2 )
Q0
Q2
Hi- Z
Q4
Hi-Z
Q6
Q7
Q8
Hi- Z
DQ(CL3)
Q1
Hi-Z
Q3
Hi-Z
Q5
Q6
Q7
*Note : 1. There are 4 DQMi (i = 0~3). Each DQMi masks 8 DQ's. (1 Byte, 1 Pixel for 8bpp). 2. DQM masks data out Hi-Z after 2 clocks which should masked by CKE "L".
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3. CAS Interrupt (I)
*Note1 1)Rea d inte r rup ted by Read (B L=4)
M32L1632512A
CLK CMD
RD
RD
AD D
A
B
DQ ( C L2 )
QA0
QB0 QA0
QB1 QB2
QB3
DQ( CL3)
QB0
QB1
QB2
QB3
tCC D
* N ot e 2
2) Wr i te in t er r upte d by( B lo ck ) W r it e ( BL= 2)
3)W r it e i n te r r upted by Re ad ( B L=2 )
CLK
CM D
WR
WR
* Note 2
WR
BW
* Note 2
WR
RD
*No te 2
tCCD
AD D A
tCCD
A
tC CD
A
B
B
* N ot e 4
B
DQ
DA0
DB0
DB1
DC 0 Pixel
DQ(CL2)
DA0
DB0
D B1
tC DL
*N ote 3
tCDL
*N ote 3
DQ( CL 3)
DA0
D B0
D B1
tCDL
4) Bl ock Wr i te to B lock Wr it e *Note 3
CLK NOP
CM D AD D
BW
BW
Note 7
A
X
B
Note 4
DQ
Pi xe l
Pixel
tBWC
*N ote 6
*Note : 1. By "Interrupt", It is possible to stop burst read/write by external before the end of burst. By " CAS Interrupt", to stop burst read/write by CAS access ; read, write and block write. 2.tCCD : CAS to CAS delay.(=1CLK) 3.tCDL : Last Data in to new column address delay.(=1CLK) 4.Pixel : Pixel mask. 5.tCC : Clock cycle time. 6.tBWC : Block write minimum cycle time. 7.Other Bank can be active or precharge.
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4. CAS Interrupt ( ) : Read Interrupted by Write & DQM
(1) CL=2, BL=4
CLK i)CMD DQ M RD WR
M32L1632512A
DQ RD
D0
D1
D2
D3
ii)CMD DQ M
WR
DQ iii)CMD RD
Hi- Z
D0
D1 WR
D2
D3
D QM Hi-Z D2
DQ iv)CMD D QM
D0
D1 WR
D3
RD
DQ
Q0
Hi- Z
*No te1
D0
D1
D2
D3
(2) CL=3 , BL=4
C LK i)CMD D QM RD WR
DQ
D0
D1
D2
D3
ii)CMD D QM
RD
WR
DQ
D0
D1
D2
D3
iii)CMD D QM
RD
WR
DQ i v) C M D D QM RD
D0
D1
D2
D3
WR
DQ RD
Hi-Z
D0
D1 WR
D2
D3
v) C M D DQM
Hi- Z DQ Q0
* No t e 2
D0
D1
D2
D3
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out. 2. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
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5. Write Interrupted by Precharge & DQM
CLK CMD
*Note2
M32L1632512A
WR
PRE
*Note 1
DQM DQ D2 D3
Maske d by DQM
D0
D1
*Note : 1. To inhibit invalid write, DQM should be issued. 2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual banks operation.
6. Precharge
1) Normal Write (BL = 4)
CLK CMD WR PRE CLK CMD BW P i xel PRE
2) Block Write
DQ
D0
D1
D2
D3
DQ
tRDL
*Note1
tBPL
*Note 1
3) Read (BL=4)
CLK CMD PRE
*No te 2
RD
1 DQ(CL2) Q0 Q1 Q2 Q3
DQ(C L3 )
Q0
Q1
Q2
Q3
2
7. Auto Precharge
1) Normal Write (BL = 4)
CLK CMD C LK C MD DQ
2) Block Write
WR D0 D2 D3
*Note3
BW
DQ
D1
P i xe l
tBPL
Auto Precharge starts
tRP tBAL
*Note3
Auto Precharge starts
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3) Read (BL=4)
CLK CMD RD
M32L1632512A
DQ ( C L 2 )
Q0
Q1
Q2
Q3
DQ(CL3 )
Q0
Q1
Q2
*Note3
Q3
Auto Precha rge sta rts
*Note : 1. tRDL : Write data-in to PRE command delay, tBPL : Block Write data-in to PRE command delay. 2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively. 3. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal. 4. For -5S/-6S/-7S/-8S, auto precharge after a normal write starts at clock(n+BL+1).
8. Burst Stop & Precharge Interrupted
1) Write interrupted by Precharge (BL=4)
CLK CMD PRE
2) Write Burst Stop (Full Page Only)
CLK CMD STOP
WR
WR
DQM DQ DQ
D0
D1
D2
D3
*Note 1
D0
D1
D2
tRDL
tB DL
3) Read interrupted by Precharge (BL=4)
CLK CMD RD PRE
*Note 3
4) Read Burst Stop (Full Page Only)
CLK CMD RD STOP 1
*Note 3
DQ(CL2)
Q0
Q1
1
DQ(CL2) 2
Q0
Q1
DQ( C L3 )
Q0
Q1
DQ(CL3)
Q0
Q1
2
9. MRS & SMRS
1) Mode Register Set
CLK
*Note4
2) Special Mode Register Set
CLK CMD SMRS ACT SMR SSMR S ACT
CMD
PRE
MRS
ACT
tRP
1CLK
1CLK
1 CLK
1CLK
1CLK
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M32L1632512A
*Note: 1. tRDL : 1 CLK ; Last data in to Row Precharge. 2. tBDL : 1 CLK ; Last data in to Burst Stop Delay. 3. Number of valid output data after Row Precharge or burst stop : 1, 2 for CAS latency = 2, 3 respectively. 4. PRE : Both banks precharge, if necessary. MRS can be issued only at all banks precharge state.
10. Clock Suspend Exit & Power Down Exit
1) Clock Supend (=Active Power Down) Exit
CLK CKE Internal C LK C MD RD
2) Power Down (=Precharge Power Down) Exit
CLK CKE Inter nal CLK CMD
tSS
*No te 1
tS S
*No te 2
NOP
AC T
11. Auto Refresh & Self Refresh
*Note3
1) Auto Refresh
CLK
*N o te 4 * No te 5
CMD
PRE
AR
CMD
CKE
tRP
tRC
1) Self Refresh *Note6
CLK
* No te 4
CMD
PRE
SR
CMD
CKE
tRP
tRC
*Note : 1. Active power down : one or more banks active state. 2. Precharge power down : both banks precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after Auto Refresh command. During tRC from auto refresh command, any other command can not be accepted. 4. Before executing auto/self refresh command, both banks must be idle state. 5. (S)MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. 6. During self refresh mode, refresh interval and refresh operation are performed internally. After self refresh entry, self refresh mode is kept while CKE is low.
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12. About Burst Type Control
Basic Mode
M32L1632512A
During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state. During tRC from self refresh exit command, any other command can not be accepted. Before/After self refresh mode, burst auto refresh (2K cycles) is recommended.
Sequential Counting At MRS A3="0". See the BURST SEQUENCE TABLE. (BL=4, 8) BL=1, 2, 4, 8 and full page wrap around. Interleave Counting At MRS A3="1". See the BURST SEQUENCE TABLE. (BL=4, 8) BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting
PseudoMODE
At MRS A3="1". (See to interleave Counting Mode) Staring Address LSB 3 bits A 0-2 should be "000" or "111". @BL=8 - if LSB ="000" : Increment Counting. Pseudo- if LSB ="111" : Decrement Counting. Document Sequential For Example, (Assume Addresses except LSB 3 bits are all 0, BL=8) Counting -- @ write, LSB ="000", Accessed Column in order 0-1-2-3-4-5-6-7 -- @ read, LSB ="111", Accessed Column in order 7-6-5-4-3-2-1-0 At BL=4, same applications are possible. As above example, at interleave Counting mode, by confining starting address to some value, Pseudo-Decrement Counting Mode can be realize. See the BURST SEQUENCE TABLE carefully. At MRS A3="0". (See to Sequential Counting Mode) A0-2 ="111". (See to Full Page Mode) Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be realize. -- @ Sequential Counting, Accessed Column in order 3-4-5-6-7-1-2-3 (BL=8) -- @ Pseudo-Binary Counting Accessed Column in order 3-4-5-6-7-8-9-10 (Burst Stop command) Note. The next column address of 256 is 0. Every cycle Read/Write Command with random column address can realize Random Column Access That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
PseudoBinary Counting
Random MODE
Random column Access tCCD = 1 CLK
13. About Burst Length Control
1 Basic MODE 2 4 8 Full Page At MRS A2, 1, 0 ="000". At auto precharge, tRAS should not be violated. At MRS A2, 1, 0 ="001". At auto precharge, tRAS should not be violated. At MRS A2, 1, 0 ="010". At MRS A2, 1, 0 ="011". At MRS A2, 1, 0 ="111". Wrap around mode (Infinite burst length) should be stopped by burst stop. RAS interrupt or CAS interrupt.
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Special MODE BRSW Block Write
M32L1632512A
At MRS A9 ="1" Read Burst =1, 2, 4, 8, full page/write Burst =1 At auto precharge of write, tRAS should not be violated. 8 Column Block Write. LSB A0-2 are ignored. Burst length =1
tRAS should not be violated. At auto precharge, tRAS should not be violated. tBDL =1, Valid DQ after burst stop is 1, 2 for CL=2, 3 respectively. Using burst stop command, random mode it is possible only at full page burst length.
Before the end of burst, Row precharge command of the same bank stops read/write burst with Row precharge. tRDL =1 with DQM, valid DQ after burst stop is 1, 2 for CL = 2, 3 respectively During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst or block write. During read/write burst with auto precharge, CAS interrupt can not be issued.
Random MODE
Burst Stop
Interrupt MODE
RAS interrupt (Interrupted by Precharge)
CAS Interrupt
14. Mask Function
1) Normal Write I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data. If bit plane 0, 3, 7, 9, 19, 22, 24 and 31 keep the original value. i) STEP I SMRS(LMR) : Load mask [31-0]="0111, 1110, 1011, 0111, 1111, 1101, 0111, 0110" II Row Active with DSF "H" : Write Per Bit Mode Enable III Perform Normal Write i) ILLUSTRATION I/O (=DQ) External Data-in DQMi Mask Register Before Write After Write 31 24 11111111 DQM3=0 01111110 00000000 01111110 23 16 11111111 DQM2=0 10110111 00000000 10110111 15 8 00000000 DQM1=0 11111101 11111111 00000010 7 0 00000000 DQM0=1 01110110 11111111 11111111 Note 1
2) Block Write Pixel masking : By Pixel Data issued through DQ pin, the selected pixels keep the original data. See PIXEL TO DQ MAPPING TABLE. If Pixel 0, 4, 9, 13, 18, 22, 27 and 31 keep the original white color. Assume 8bpp White = "0000, 0000", Red = "1010, 0011", Green = "1110, 0001", Yellow = "0000, 1111", Blue = "1100, 0011" i) STEP I SMRS(LCR) : Load color (for 8bpp, through x32 DQ color0-3 are loaded into color registers) Load (color3, color2, color1, color0) = (Blue, Green, Yellow, Red) = "1100, 0011, 1110, 0001, 0000, 1111, 1010, 0011 " II Row Active with DSF "L" : I/O Mask by Write Per Bit Mode Disable III Block write with DQ[31-0] = "0111, 0111, 1011, 1011, 1101, 1101, 1110, 1110" * Note : 1. DQM byte masking.
Elite Semiconductor Memory Technology Inc.
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(Continued)
i) ILLUSTRATION I/O (=DQ) DQMi Color Register 000 Before Block Write & DQ (Pixel data) 001 010 011 100 101 110 111 000 001 After Block Write 010 011 100 101 110 111 Note 1 31 24 23 16 15 DQM1=0 Color1=Yellow White DQ8=H White DQ9=L White DQ10=H White DQ11=H White DQ12=H White DQ13=L White DQ14=H White DQ15=H Yellow White Yellow Yellow Yellow White Yellow Yellow 8 7 DQM3=0 Color3=Blue White DQ24=H White DQ25=H White DQ26=H White DQ27=L White DQ28=H White DQ29=H White DQ30=H White DQ31=L Blue Blue Blue White Blue Blue Blue White DQM2=0 Color2=Green White DQ16=H White DQ17=H White DQ18=L White DQ19=H White DQ20=H White DQ21=H White DQ22=L White DQ23=H Green Green White Green Green Green White Green
M32L1632512A
0 DQM0=1
Color0=Red White DQ0=L White DQ1=H White DQ2=H White DQ3=H White DQ4=L White DQ5=H White DQ6=H White DQ7=H White White White White White White White White
Pixel and I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data. By Pixel Data issued through DQ pin, the selected pixels keep the original data. See PIXEL TO DQ MAPPING TABLE. Assume 8bpp, White = "0000, 0000", Red = "1010, 0011", Green = "1110, 0001", Yellow = "0000, 1111", Blue = "1100, 0011" i) STEP I SMRS(LCR) : Load color (for 8bpp, through x 32 DQ color0-3 are loaded into color registers) Load (color3, color2, color1, color0, ) = (Blue, Green, Yellow, Red) ="1100, 0011, 1110, 0001, 0000, 1111, 1010, 0011" II SMRS(LMR) Load mask. Mask[31-0] = "1111.1111. 1101, 1101, 0100, 0010, 0111, 0110" Byte 3 : No I/O Masking ; Byte 2 : I/O Masking ; Byte 1 : I/O and Pixel Masking ; Byte 0 : DQM Byte Masking III Row Active with DSF "H" : I/O mask by Write Per Bit Mode Enable IV Block Write with DQ [31-0] = "0111, 0111 .1111, 1111, 0101, 0101, 1110, 1110 "(Pixel Mask)
AE
*Note : 1. At normal write, ONE column is selected among columns decorded by A2-0 (000-111). At block write, instead of ignored address A2-0, DQ0-31 control each pixel.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001 Revision : 1.6 28/54
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i) ILLUSTRATION I/O (=DQ) Color Register DQMi Mask Register Before Write After Write 31 24 23 16 15 6 Blue 11000011 DQM3=0 11111111 Yellow 00001111 Blue 11000011 Green 11100001 DQM2=0 11011101 Yellow 00001111 Blue 11000011 Yellow 00001111 DQM1=0 01000010 Green 11100001 Red 10100011
M32L1632512A
7
0
Red 10100011 DQM0=1 01110110 White 00000000 White 00000000
I/O (=DQ) DQMi Color Register 000 Before Block Write & DQ (Pixel data) 001 010 011 100 101 110 111 000 001 After Block Write 010 011 100 101 110 111 Note 2
31 DQM3=0
24
23 DQM2=0
16
15 DQM1=0
6
7 DQM0=1
0
Color3=Blue Yellow DQ24=H Yellow DQ25=H Yellow DQ26=H Yellow DQ27=L Yellow DQ28=H Yellow DQ29=H Yellow DQ30=H Yellow DQ31=L Blue Blue Blue Yellow Blue Blue Blue Yellow
Color2=Green Yellow DQ16=H Yellow DQ17=H Yellow DQ18=H Yellow DQ19=H Yellow DQ20=H Yellow DQ21=H Yellow DQ22=H Yellow DQ23=H Blue Blue Blue Blue Blue Blue Blue Blue
Color1=Yellow Green DQ8=H Green DQ9=L Green DQ10=H Green DQ11=L Green DQ12=H Green DQ13=L Green DQ14=H Green DQ15=L Red Green Red Green Red Green Red Green
Color0=Red White DQ0=L White DQ1=H White DQ2=H White DQ3=H White DQ4=L White DQ5=H White DQ6=H White DQ7=H White White White White White White White White Note 1
PIXEL MASK
I/O MASK
PIXEL & I/O MASK
BYTE MASK
*Note : 1. DQM byte masking. 2. At normal write, ONE column is selected among columns decorded by A2-0(000-111) At block write, instead of ignored address A2-0, DQ0-31 control each pixel.
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FUNCTION TRUTH TABLE (TABLE 1)
Current State CS RAS CAS WE DSF H L L L L L L L L L L L H L L L L L L L L L L L L H L L L L L L L L L L L H L L L L L L L X H H H L L L L L L L L X H H H H H H L L L L L L X H H H H H H H L L L L X H H H H H H H X H H L H H H H L L L L X H H L L L L H H H L L L X H H H L L L L H H H L X H H H L L L L X H L X H H L L H H L L X H L H H L L H L L H L L X H L L H H L L H L L X X H L L H H L L X X X X L H L H L H L H X X X L H L H X L H X L H X X L H L H L H X L H X X X L H L H L H BA ADDR (A10) X X X X X X BA CA BA RA BA RA X PA BA X X X BA X OP Code OP Code X X X X X X BA CA, AP X X BA CA, AP BA CA, AP BA RA BA RA X X X X X X OP Code X X X X X X X X BA CA, AP X X BA CA, AP BA CA, AP BA RA BA PA X X X X X X X X X X X X BA CA, AP X X BA CA, AP BA CA, AP
M32L1632512A
ACTION NOP NOP ILLEGAL ILLEGAL Row Active ; Latch Row Address ; Non-IO Mask Row Active ; Latch Row Address ; IO Mask Auto Refresh or Self Refresh NOP Auto Refresh or Self Refresh ILLEGAL Mode Register Access Special Mode Register Access NOP NOP ILLEGAL Begin Read ; Latch CA ; Determine AP ILLEGAL Begin Write ; Latch CA ; Determine AP Begin Write ; Latch CA ; Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL ILLEGAL Special Mode Register Access NOP (Continue Burst to End Row Active) NOP (Continue Burst to End Row Active) Term burst Row active ILLEGAL Term burst, Begin Read ; Latch CA ; Determine AP ILLEGAL
Note
2 2
IDLE
4 5 5 6
2
Row Active
2
AE
AE AE
6
3 3 3 2 3
Read
Term burst, Begin Write ; Latch CA ; Determine AP Term burst, Begin Write ; Latch CA ; Determine AP
Write
ILLEGAL Term Burst, Precharge timing for Reads ILLEGAL ILLEGAL NOP (Continue Burst to End Row Active) NOP (Continue Burst to End Row Active) Term burst Row Active ILLEGAL Term burst, Begin Read ; Latch CA ; Determine AP ILLEGAL
AE
AE AE
3 3 3
Term burst, Begin Write ; Latch CA ; Determine AP Term burst, Begin Write ; Latch CA ; Determine AP
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FUNCTION TRUTH TABLE (TABLE 1, Continued)
Current State Write CS RAS CAS WE DSF BA (A10) BA BA X X X X X BA BA BA X X X X BA BA BA X X X X BA BA BA X X X X BA BA BA X X X X BA BA BA X X X X X X ADDR RA RA X X X X X CA, AP CA, AP RA, PA X X X X CA, AP CA, AP RA, PA X X X X CA, AP RA PA X X X X CA, AP RA PA X X X X CA, AP RA PA X X X X X X L L H H X L L H L L L L H H H L L L X X H X X X X L H H H X Read with L H H L X Auto L H L H X Precharge L H L L X L L H X X L L L X X H X X X X L H H H X Write with L H H L X Auto L H L H X Precharge L H L L X L L H X X L L L X X H X X X X L H H H X L H H L X Precharging L H L X X L L H H X L L H L X L L L X X H X X X X L H H H X Block L H H L X Write L H L X X Recovering L L H H X L L H L X L L L X X H X X X X L H H H X Row L H H L X Activating L H L X X L L H H X L L H L X L L L X X H X X X X L H H X X Refreshing L H L X X L L H X X L L L X X ABBREVIATIONS : RA = Row Address (A0~A9) NOP = No Operation Command
M32L1632512A
ACTION ILLEGAL Term Burst : Precharge timing for Writes ILLEGAL ILLEGAL NOP(Continue Burst to End Precharge) NOP(Continue Burst to End Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Continue Burst to End Precharge) NOP(Continue Burst to End Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP Idle after tRP NOP Idle after tRP ILLEGAL ILLEGAL ILLEGAL NOP Idle after tRP ILLEGAL NOP Row Active after tBWC NOP Row Active after tBWC ILLEGAL ILLEGAL ILLEGAL
Note 2 3
AE AE AE AE
2 2 2
2 2 2
AE AE AE AE AE AE AE AE AE
2 2 2 4
Term Block Write : Precharge timing for Block Write
ILLEGAL NOP Row Active after tRCD NOP Row Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP Idle after tRC NOP Idle after tRC ILLEGAL ILLEGAL ILLEGAL
2 2 2 2
2 2 2 2
BA = Bank Address (A10) CA = Column Address (A0~A7)
PA = Precharge All (A9) AP = Auto Precharge (A9)
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FUNCTION TRUTH TABLE (TABLE 1, Continued)
M32L1632512A
*Note : 1. All entries assume the CKE was active (High) during the preceding clock cycle and the current clock cycle. 2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and PA). 5. Illegal if any bank is not idle. 6. Legal only if all banks are in idle or row active state.
FUNCTION TRUTH TABLE for CKE (TABLE2)
Current State CKE ( n-1 ) H L L CKE n X H H CS RAS CAS WE DSF ADDR X H L X X H X X H H L X X X X H H L X X X X H H L H L L X X X X X X X H L X X X X X H L X X X X X H L X X H L X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X ACTION INVALID Exit Self Refresh after tRC Exit Self Refresh after tRC ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down Exit Power Down ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Low Power Mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend Note 7 7
Self Refresh
L H L H L H L H L H L L L L X X H X X X Both L H H X Bank L H L H Precharge L H L H Power L H L H Down L H L L L L X X H H X X H L H X H L L H All H L L H Banks H L L H Idle H L L L H L L L H L L L L L X X Any State H H X X other than H L X X Listed L H X X Above L L X X ABBREVIATIONS : ABI = All Banks Idle
AEAAE AEAAE
AEABI AEABI
8 8
9 9
9
10 10
*Note : 7.After CKE's low to high transition to exit self refresh mode. And a time of tRC(min) has to be elapse after CKE's low to high transition to issue a new command. 8.CKE low to high transition is asynchronous as if restart internal clock. A minimum setup time " tSS + one clock " must be satisfy before any command other than exit. 9.Power down and self refresh can be entered only from the all banks idle state. 10.Must be a legal command.
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Power On Sequence & Auto Refresh
0 CLOC K 1 2 3 4 5 6 7 8 9 10 11 12 13 14
M32L1632512A
15
16
17
18
19
CKE
H i g h l e v el i s n e c es s a r y
CS
tRP
RAS
tRC
CAS
ADDR
KE Y
Ra
A10 /B A
KE Y
BS
A9 /A P
KEY
Ra
WE
DSF
DQ M
H i g h l e v el i s n e c e s s a r y
High- z DQ
Precharge (All Bank s)
A u to R ef r e s h
A u t o R e f r es h
Mode Register Set Row Ac tive ( W r i t e P er B i t Enable or D isable)
:D on't C ar e
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tCH
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14
M32L1632512A
Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency = 3, Burst Length = 1
15 16 17 18 19
tCL tC C
CKE HIGH
t RAS tRC
*Note 1
t SH tSS tRP
CS
tRCD tSH
RAS
tS S tSH
CAS
tCCD
tSS tSH
ADDR Ra Ca
tS S
Cb Cc Rb
tSS
*Note 2 *No t e 2, 3
tSH
*Note2, 3 *No t e 2, 3 *Note 4 *Not e 2
A1 0
BS
BS
BS
BS
BS
BS
*Not e 3
*Note 3
*Not e 3 *Not e 4
A9
Ra
Rb
tSH
WE
tS S
*Not e 5 *Note6 * No t e 5
DSF
tSS
DQM
tSH tS S tSH
t RAC tSAC
DQ Qa Db
tSH
Qc
tSLZ
tOH t SHZ
tS S
Row Acti ve Read (W rite per Bit Enable or Dis able)
W rite or Bloc k W r it e
Read Precharge Row Ac t ive (W ri te Per B it E n a b l e o r D i s a bl e )
:D on't C are
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M32L1632512A
* Note : 1. All input can be don't care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by A10.
A10 0 1
Active & Read/Write Bank A Bank B
3. Enable and disable auto precharge function are controlled by A9 in read/write command.
A9 0 1 A10 0 1 0 1 Operation Disable auto precharge, leave bank A active at end of burst. Disable auto precharge, leave bank B active at end of burst. Enable auto precharge, precharge bank A at end of burst. Enable auto precharge, precharge bank B at end of burst.
4. A9 and A10 control bank precharge when precharge command is asserted.
A9 0 0 1 A10 0 1 X Precharge Bank A Bank B Both Bank
5. Enable and disable Write-per Bit function are controlled by DSF in Row Active command.
A10 0 1 DSF L H L H Operation Bank A row active, disable write per bit function for bank A. Bank A row active, enable write per bit function for bank A. Bank B row active, disable write per bit function for bank B. Bank B row active, enable write per bit function for bank B.
6. Block write/normal write is controlled by DSF.
DSF L H Operation Normal write Block write Minimum cycle time
tCCD tBWC
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Read & Write Cycle at Same Bank @ Burst Length = 4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 HIGH CKE
*No te 1
M32L1632512A
15
16
17
18
19
tRC
CS
tRC D
RAS
*Not e2
CAS
ADDR
Ra
Ca0
Rb
Cb0
A1 0
A9
Ra
Rb
WE
DSF
DQM
tOH
DQ CL=2 Qa0 Q a1 Qa2 Qa3 D b0 D b1 D b2 Db3
tR AC
*Not e 3
tSAC tO H
Q a0 Qa1 Qa2
tSHZ
Q a3
*Note 4
tRDL
CL = 3
Db0
Db1
Db2
Db3
tRAC
*Note3
tS AC
t S H Z *N ot e 4
tRDL
Row Act ive (A-Bank)
R ea d (A-Ban k)
Precharge ( A - B an k )
Row Ac tive (A- Bank )
W rite (A-Bank)
Pre ch arg e ( A - B an k )
:Don't C are
*Note :
1. Minimum row cycle time is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle.[CAS Length - 1] valid output data available after Row. enters Hi-Z after tSHZ from the clock. 3. Access time from Row address. tCC *( tRCD +CAS latency - 1) + 4. Output will be Hi-Z after the end of burst. (1, 2, 4 & 8) At Full page bit burst, burst is wrap-around.
precharge. Last valid output will be
tSAC
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Page Read & Write Cycle Same Bank @ Burst Length = 4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 HIGH CKE
M32L1632512A
15
16
17
18
19
CS
tRCD
RAS
*Note 2
CAS
AD DR
Ra
Ca0
Cb0
Cc0
C d0
A1 0
A9
Ra
t CDL
WE
*Note 2
tRDL
DSF
*Note 1
*Note 3
DQM
DQ
C L= 2
Qa0
Qa1
Q b0
Q b1
Dc0
Dc1
Dd0
Dd1
CL = 3
Qa0
Q a1
Qb0
Dc0
Dc1
D d0
Dd1
Row Ac ti ve ( A - B an k )
Rea d (A-Bank )
Rea d (A-Bank )
W rit e (A-Bank)
Write ( A - Ba n k )
Pre char ge ( A - B an k )
:Don't C are
* Note : 1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.
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Block Write cycle (with Auto Precharge)
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 HIGH CK E
M32L1632512A
15
16
17
18
19
CS
RAS
CAS
*Note 4
ADDR
RAa
CAa
CA b
RBa
CBa
CB b
A10
A9
RAa
RBa
WE
DSF
*Note 2
tBWC
DQM
*Not e 3 *Note1
DQ
P i xe l Ma sk
P ixel Mask
Pixel Mask
P ixel Mask
Ro w Ac t i ve w i t h W ri te-per- Bit E n ab l e ( A- Ba n k )
Mas ked Bl o c k W r i t e ( A - B an k ) M asked Bl ock W r i t e w i th Au to Pr ech ar ge ( A- Ba n k)
R ow Ac t i ve ( B- Ban k )
Block W rit e wit h Auto P rechar ge ( B- Ba n k ) Block W r ite ( B- Ban k )
:Don't Care
*Note : 1. Column Mask (DQi = L : Mask, DQi = H : Non Mask) 2. tBWC : Block Write Cycle time 3. At Block Write, second cycle should be in NOP. Other Bank can be active or precharge. 4. At Block Write. CA0-2 are ignored.
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SMRS and Block/Normal Write @ Burst Length = 4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HIGH CKE
M32L1632512A
16 17 18 19
CS
RAS
CAS
*N ot e1
A0-2
RAa
RBa
CBa
A3,4 ,7, 8
RAa
CAa
RB a
CB a
A5
RA a
CA a
RB a
CBa
A6
RA a
CAa
RB a
CBa
A9
RAa
RBa
A9
WE
DSF
DQ M
DQ
Color
I/O Mask
Pi xe l Mask
I/O Mask
Color
D Ba 0 DB a1 D Ba 2 DB a3
Load Color Regis ter
L oad M as k Regist er
Ro w A ct i ve wi th W PB* E n ab l e ( A - B an k )
Ro w A c t i v e L oa d C o l o r w i t h W PB * R e g i s t e r En a bl e Masked Ma ske d W r i t e ( B - B an k ) Bl o c k W r i t e wi t h Au t o ( A - B an k ) P r ec h ar g e Load Mask Regi st er ( B- Ba n k )
W P B * : W r i t e- P e r - B i t :D on' t Car e
*Note : 1. At the next clock of special mode register set command, new command is possible.
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Page Read Cycle at Different Bank @ Burst Length = 4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HIGH CKE
* No t e1
M32L1632512A
16
17
18
19
CS
RAS
*N ot e2
CAS
ADDR
RAa
CAa
RBb
CBb
CAc
CB d
CA e
A1 0
A9
RAa
RBb
WE
DSF
LO W
DQ M
DQ
CL= 2
Q A a 0 Q Aa 1 Q A a 2 Q Aa 3 Q B b 0 Q B b 1 Q Bb 2 Q B b 3 Q A c 0 Q A c 1 Q B d 0 Q B d 1 Q A e 0 Q A e 1
CL = 3
Q Aa 0 Q A a 1 Q A a 2 Q A a 3 Q B b 0 Q B b 1 Q B b 2 Q B b 3 Q A c 0 Q A c 1 Q B d 0 Q Bd 1 Q A e 0 Q A e 1
Row Act i ve ( A - B an k )
Ro w A cti ve ( B - B an k ) Read ( A - Ba n k )
Read ( B - Ba n k )
Read ( A - Ba n k )
Read ( B - Ba n k )
Rea d (A-Bank)
Pr e ch a r g e ( A- B an k )
:D on' t Car e
*Note : 1. CS can be don't care when RAS , CAS and WE are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
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Page Write Cycle at Different Bank @ Burst Length =4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 HIGH CKE
M32L1632512A
15
16
17
18
19
CS
RAS
CAS
ADDR
RAa
Ke y
CA a
RB b
CBb
CAc
CBd
A1 0
A9
RAa
RB b
tCDL
WE
DSF
DQ M
DQ
Mask
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 D Bb3 DAc 0 D Ac 1 DAc 2 DAc 3 DBd0 DBd1 DBd2 D Bd3
Load M as k Regis t er Ro w Ac t i ve w i t h Wr ite-Per- Bit enable (A- Ba n k)
Row Ac t iv e ( B- Ban k ) Mas ked W ri t e ( A- Ba n k)
W ri t e ( B- Ba n k )
M as ked W r i t e wi th aut o pr echar ge ( A- Ban k )
W ri te w i th aut o Pr ech arge ( B- Bank )
: Don't Car e
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Read & Write Cycle at Different Bank @ Burst Length =4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 HIG H CKE
M32L1632512A
15
16
17
18
19
CS
RAS
CAS
ADDR
RAa
CAa
RBb
CBb
RA c
CAc
A1 0
A9
RAa
RBb
RAc
t CD L
WE
*Not e 1
DSF
DQ M
DQ CL=2
Q Aa 0 Q Aa 1 Q A a2 QA a 3
DBb0 DBb1 DBb2 DBb3
QA c 0 Q A c 1 Q A c 2
CL=3
Q Aa 0 Q Aa 1 Q Aa 2 Q A a3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1
Row Ac t ive (A-Bank )
R ea d (A-Bank )
Precharge ( A - B an k ) Row Active ( B-Ban k)
W rite (B-Ban k ) Row A ctive ( A - B an k )
Rea d (A- Bank )
:Don't Car e
*Note : 1. tCDL should be met to complete write.
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Read & Write Cycle with Auto Precharge @ Burst Length =4
0 CLOC K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 HIGH CKE
M32L1632512A
15
16
17
18
19
CS
RAS
CAS
ADDR
Ra
Rb
Ca
Cb
A1 0
A9
Ra
Rb
WE
DSF
DQ M
DQ CL= 2
Qa0
Qa1
Q a2
Qa3
Db0
Db1
Db2
Db3
CL = 3
Qa0
Q a1
Qa2
Q a3
Db0
Db1
Db2
Db3
Ro w A ct i ve (A-Bank)
R ea d w i t h A u t o P r ec h ar g e (A- Bank) Row Active ( B - B an k )
A u o t P r ec h ar g e S t a r t P oi n t (A- Bank)
W r i te wi t h A u t o P r ec h ar g e (B- Bank )
A u ot P r e c h a r g e S t ar t P o i n t (B-Bank )
:D on't C ar e
*Note : 1. tRDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length = 1 & 2, BRSW mode and Block write)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001 Revision : 1.6 43/54
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Read & Write Cycle with Auto Precharge II @ Burst Length =4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HIGH CK E
M32L1632512A
16
17
18
19
CS
RAS
CAS
ADDR
Ra
Rb
Ca
Cb
Ra
Ca
A1 0
A9
Ra
Rb
Ra
WE
DSF
DQM
DQ CL =2
Q a0
Q a1
Q b0
Qb1
Db2
D b3
Da0
Da1
Q a0
Qa1
Q b0
Qb1
Db2
D b3
Da0
Da1
Row Act i ve (A-Bank)
Rea d w i t h A u t o P r ec h ar g e ( A- B a n k ) Row A cti ve ( B - B an k ) Re ad wi t h o u t A u t o P r ec h a r g e ( B - B an k ) Au toP r e ah ar g e St ar t Poi n t (A-Bank)
Precharge ( B- B an k )
Row A cti ve ( A - B an k )
W r ite wi th Au o t P r ech a r g e ( A- B a n k )
:Don't Care
*Note : 1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation. - If Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank auto precharge will start at the next cycle of B Bank read command input point. - any command can not be issued at A Bank during tRP after A Bank auto precharge starts.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001 Revision : 1.6 44/54
$%
Read & Write Cycle with Auto Precharge EEE @ Burst Length =4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 HIG H CKE
M32L1632512A
15
16
17
18
19
CS
RAS
CAS
ADDR
Ra
Ca
Rb
Cb
A1 0
A9
Ra
Rb
WE
DSF
tRC D
DQ M
DQ CL=2
Qa0
Q a1
Q a2
Q a3
Db0
Db1
Db2
Db3
CL=3
Q a0
Q a1
Qa2
Q a3
Db0
Db1
Db2
Db3
*N ot e 1
Row Ac t ive (A-Bank )
Read w it h Auto Precharge (A-Bank )
R ea d w i t h A u o t P r e c h ar g e A u t o P r e c h ar g e Start Poin t (B- Bank ) (A- Bank ) Ro w A c ti ve (B- Bank )
A u o t P r e c h ar g e Start Poin t (B- Bank )
:Don't Car e
*Note : 1. Any command to A Bank is not allowed in this period. tRP is determined from at auto precharge start point.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001 Revision : 1.6 45/54
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0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
M32L1632512A
Read Interrupted by Precharge Command & Read Burst Stop Cycle (@ Full Page Only)
16 17 18 19
HI GH CKE
CS
RAS
CAS
AD DR
RAa
CA a
CAb
A1 0
*N ot e 1 *Not e 1
A9
RAa
WE
DSF
DQM
DQ C L=2
*N ot e 2 1 Q Aa 0 Q A a 1 Q A a 2 Q A a 3 Q A a 4
1 D Ab0 DA b1 DA b2 D Ab 3 DAb 4 DA b5
CL= 3
2 Q A a 0 Q A a 1 Q A a 2 Q A a 3 Q Aa 4
2 D Ab 0 DAb 1 DA b2 DA b3 DA b4 D Ab 5
Row Active ( A - B an k )
Rea d (A-Bank)
B u r st St o p
Rea d (A-Bank)
Precharge (A-Bank)
:Don't Care
*Note : 1. At full page mode, burst is warp-around at the end of burst. So auto precharge is impossible. 2. About the valid DQ's after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1, 2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of "Full page write burst stop cycle". 3. Burst stop is valid at full page mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001 Revision : 1.6 46/54
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0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HIGH CKE
M32L1632512A
Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Full Page Only)
16 17 18 19
CS
RAS
CAS
ADDR
RA a
CAa
CAb
A1 0
*N ot e 1 *N ot e 1
A9
RA a
tBDL
WE
tRDL
D SF
*No te 3
DQ M
*No te 2
DQ
D A a0 D A a 1 D A a 2 D A a3 DA a 4
D Ab 0 DA b 1 D A b2 DA b 3 DA b 4 D A b5
Row Ac t i ve ( A - B an k )
W rite (A-Bank )
Burst Stop
W rite (A-Bank )
Precharge ( A - B an k )
:Don't Care
*Note : 1. At full page mode, burst is warp-around at the end of burst. So auto precharge is impossible. 2. Data-in at the cycle of burst stop command cannot be written into the corresponding memory cell. It is defined by AC parameter of tBDL (=1CLK). 3. Data-in at the cycle interrupted by precharge cannot be written into the corresponding memory cell. It is defined by AC parameter of tRDL (=1CLK). DQM at write interrupted by precharge command is needed to ensure tRDL of 1CLK. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 4. Burst stop is valid only at full page burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001 Revision : 1.6 47/54
$%
Burst Read Single bit Write Cycle @ Burst Length = 2, BRSW
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
*Not e 1
M32L1632512A
16
17
18
19
HIGH
CKE
CS
RAS
*Not e 2
CAS
ADDR
RA a
CAa
RBb
CA b
RA b
C Bc
CAd
A1 0
A9
RA a
RBb
RAc
WE
D SF
DQ M
QAa 0
DA b0 D Ab 1
DBc0
D A d0 D Ad 1
CL = 3
QAa0
D Ab 0 DA b1
D Bc 0
DA d 0 DA d1
Row A ct i ve ( A - B an k )
Ro w Ac ti ve ( B - B an k ) W rit e (A-Bank)
Ro w Ac ti ve ( A - B an k )
R ea d (A-Bank)
Pre ch arg e ( A - B an k )
Read w ith A u t o P r ec h a r g e (A-Bank )
W ri t e wi t h A u t o P r ec h a r g e (B-Bank ) :Don' t Car e
*Note : 1. BRSW mode is enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regardless of programed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command. The next cycle is also starts the precharge. 3. WPB function is also possible at BRSW mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001 Revision : 1.6 48/54
$%
0 CLOC K 1 2 3 4 5 6 7 8 9 10 11 12 13 14
M32L1632512A
Clock suspension & DQM operation cycle @ CAS Latency = 2, Burst Length = 4
15 16 17 18 19
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
A1 0
A9
RA
WE
DSF
*Note1
DQ M
DQ
Q a0
Qa1
Qa2
Q a3
Qb0
Q b1
Dc 0
Dc2
tSHZ
Row Ac t ive Read Cloc k S u s p en s i o n R ea d
tSHZ
W ri te DQ M
Read D QM
W r ite
Cloc k Suspension
:Don' t C ar e
*Note : 1. DQM needed to prevent bus contention.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001 Revision : 1.6 49/54
$%
0 CLOCK
*N ot e 2
M32L1632512A
Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length =4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
tS S
CKE
*Not e 1
tSS
tSS
tS S
*Not e 3
CS
RAS
CAS
ADDR
Ra
Ca
A1 0
A9
Ra
WE
DSF
DQ M
DQ
Qa0
Q a1
Q a2
P r ec h ar g e P o w er - d o w n Entr y
P r e ch ar g e P o w er - d o w n E xi t Row Active Active P o w er - d o w n Entr y
Read
Pr e ch ar ge
A cti ve P o w er - d o w n E xi t :Don't C ar e
*Note : 1. All banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at lease "1CLK + tSS" prior to Row active command. 3. Cannot violate minimum refresh specification. (32ms)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001 Revision : 1.6 50/54
$%
Self Refresh Entry & Exit Cycle
0 CLOCK
*Not e 2 *Note 4
M32L1632512A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tRCmin tSS
*Note 6
CKE
*Note 1
*N ot e 3
tS S
CS
*Note 5
RAS
*Not e 7 *Not e 7
CAS
ADDR
A10
A9
WE
DSF
DQM
DQ
Hi-Z
Hi-Z
S el f R e f r es h E n t r y
S e l f R e f r e s h E xi t
A u t o R ef r e s h
:Don't Car e
*Note : TO ENTER SELF REFRESH MODE 1. CS , RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low". cf.) Once the device enters self refresh mode minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tRC is required after CKE going high to complete self refresh exit. 7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001 Revision : 1.6 51/54
$%
Mode Register Set Cycle
0 CLOCK 1 2 3 4 5 6
M32L1632512A
Auto Refresh Cycle
0 1 2 3 4 5 6 7 8 9 10
HIGH CKE
HIGH
CS
*Not e 2
tR C
RAS
*Not e 1
CAS
*N ot e 3
ADDR
Key
Ra
WE
D SF
DQ M
DQ
Hi-Z
Hi-Z
M R S N ew Com mand
A u t o R ef r e s h
Ne w Com m an d
:Don't C ar e
*Both bank precharge should be completed Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE *Note : 1. CS , RAS , CAS & WE activation and DSF of low at the same clock cycle with address key will set internal mode register. 2. Minimum 1 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001 Revision : 1.6 52/54
$%
PACKING 100-LEAD
80
M32L1632512A
DIMENSIONS QFP(14 x 20 mm)
SEE DETAIL "A"
D D1 51 50
81
E E1
L
PIN 1
L1
DETAIL "A"
100 31 1
30
c
A
A1
A2
SEATING PLANE b
e
Symbol A A1 A2 b c D D1 E E1 L L1 e y
Dimension in mm Dimension in inch Min Norm Max Min Norm Max 3.400 0.134 0.250 0.010 2.650 2.970 0.104 0.117 0.220 0.380 0.0087 0.015 0.110 0.230 0.0043 0.009 23.000 23.200 23.400 0.906 0.913 0.921 19.900 20.000 20.100 0.783 0.787 0.791 17.000 17.200 17.400 0.669 0.677 0.685 13.900 14.000 14.100 0.547 0.551 0.555 0.650 0.800 0.950 0.026 0.031 0.037 1.600 REF 0.063 REF 0.650 REF 0.026 REF 0 0 7 7 0.080 0.003
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001 Revision : 1.6 53/54
$%
Important Notice All rights reserved.
M32L1632512A
No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001 Revision : 1.6 54/54

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